1. Field of the Invention
The present invention relates to an SOC technology, particularly to a multi-core SOC synchronization component.
2. Description of the Related Art
In a computer system, different units usually intend to access an identical piece of data synchronously. It also occurs frequently that the execution sequence of two or more programs or processes depends on the contents of an identical piece of data. The synchronization problem of two different processes may be discussed from the views of the common processor architecture and the embedded system architecture.
In the common processor architecture, such as the IntelX86, software, i.e. the operating system, handles the synchronization problem. When an operating system handles the data synchronization problem or manages the schedule of different processes, some tasks must be undertaken exclusively. In other words, only a single process is allowed to access/process a data variable or a series of steps at a time. The operating systems have several approaches to solve the synchronization problem. For example, the Linux adopts the methods of shared memory, pipe, etc., to handle the synchronization problem. The operating systems usually adopt the mass schedule control mechanism of the multi-threading function, such as the POSIX thread database of the Linux, to manage the schedule.
However, meaningless switching of processes may occur in an operation system. Suppose that a process is accessing a piece of shared data. If another process also intends to access the shared data, it will persistently query whether the shared data is accessible. If the access request is refused, the operating system will switch to a further another process, and the query will repeat. Thus, the operating system will ceaselessly switch the processes without completing any task but waste a lot of CPU resources.
In the embedded system architecture, the synchronization problem is solved by a Library method or a special hardware. Similar to the operating systems, the Library method also has the advantages of programmability and modularization. The Library method outperforms the operating systems in the execution speed but lacks security and the support from other libraries. When adopting a special hardware to solve the synchronization problem, the embedded system is benefited by hardware in speed but impaired by hardware in flexibility and expandability.
Further, meaningless overload of bus traffic may occur in the embedded system. When many components are competing for an identical resource, they all send requests to the resource. However, only a single process is allowed to use the resource at a time. Thus, the other processes will persistently send requests to the bus. Then, the bus is overloaded, and other components needing to use the bus are blocked outside and forced to stand by. The synchronization hardwares used by the embedded systems have various specifications but lack a standard interface. Thus, a new system needs a new synchronization hardware, and a lot of time and resources are wasted thereon. Most synchronization hardwares are usually designed to only support few components at a time because they lack a standard interface. A synchronization hardware does not support the components having different interfaces.
Accordingly, the present invention proposes a multi-core SOC synchronization component to overcome the abovementioned problems.